The present invention relates to the formation of a borophosphosilicate glass ("BPSG") layer during the fabrication of integrated circuits on semiconductor wafers. More particularly, the present invention relates to an improved reflow process that may reduce the thermal budget of a fabrication process while providing gap-filling properties that enable the BPSG layer to meet the requirements of modem day manufacturing processes.
Silicon oxide is widely used as an insulating layer in the manufacture of semiconductor devices. A silicon oxide film can be deposited by thermal chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) processes from a reaction of silane (SiH.sub.4), tetraethoxysilane (Si(OC.sub.2 H.sub.5).sub.4), hereinafter referred to as "TEOS," or a similar silicon-containing source, with an oxygen-containing source such as O.sub.2, ozone (O.sub.3), or the like.
One particular use for a silicon oxide film is as a separation layer between the polysilicon gate/interconnect layer and the first metal layer of MOS transistors. Such separation layers are referred to as premetal dielectric (PMD) layers because they are typically deposited before any of the metal layers in a multilevel metal structure. In addition to having a low dielectric constant, low stress and good adhesion properties, it is important for PMD layers to have good planarization and gap-fill characteristics.
When used as a PMD layer, the silicon oxide film is deposited over a silicon substrate having a lower level polysilicon gate/interconnect layer. The surface of the silicon substrate may include isolation structures, such as trenches, and raised or stepped surfaces, such as polysilicon gates and interconnects. The initially deposited film generally conforms to the topography of the substrate surface and is typically planarized or flattened before an overlying metal layer is deposited.
Several methods have been developed to fill the gaps and "planarize" or "flatten" the substrate surface. Examples include depositing a conformal layer of silicon oxide (or another material) of sufficient thickness and polishing the wafer to obtain a flat surface; depositing a conformal layer of silicon oxide (or another material) of sufficient thickness and etching the layer back to form a planarized surface; and forming a layer of relatively low-melting-point silicon oxide and then heating the substrate sufficiently to cause the layer to melt and flow as a liquid, resulting in a flat surface upon cooling. Such heating can be performed using either a rapid thermal pulse (RTP) method or conventional furnace, for example, and can be done in a dry (e.g., N.sub.2 or O.sub.2) or wet (e.g., steam H.sub.2 /O.sub.2) ambient. Each process has attributes that make that process desirable for a specific application.
Because of its low dielectric constant, low stress, good adhesion and gap-fill properties and relatively low reflow temperature, borophosphosilicate glass ("BPSG") is one silicon oxide film that has found particular applicability in applications that employ a reflow step to planarize PMD layers. Standard BPSG films are formed by introducing a phosphorus-containing source and a boron-containing source into a processing chamber along with the silicon- and oxygen-containing sources normally required to form a silicon oxide layer. Examples of phosphorus-containing sources include triethylphosphate (TEPO), triethylphosphite (TEP.sub.i), trimethylphosphate (TMOP), trimethylphosphite (TMP.sub.i), and similar compounds. Examples of boron-containing sources include triethylborate (TEB), trimethylborate (TMB), and similar compounds.
As semiconductor design has advanced, the feature size of the semiconductor devices has dramatically decreased. Many integrated circuits (ICs) now have features, such as traces or trenches that are significantly less than a micron across. While the reduction in feature size has allowed higher device density, more chips per wafer, more complex circuits, lower operating power consumption, and lower cost, the smaller geometries have also given rise to new problems, or have resurrected problems that were once solved for larger geometries.
One example of a manufacturing challenge presented by submicron devices is the ability to completely fill a narrow trench in a void-free manner. To fill a trench with BPSG, a layer of BPSG is first deposited on the patterned substrate. The BPSG layer typically covers the field, as well as the walls and bottom of the trench. If the trench is wide and shallow, it is relatively easy to completely fill the trench with BPSG. As the trench gets narrower and the aspect ratio (the ratio of the trench height to the trench width) increases, it becomes more likely that the opening of the trench will "pinch off."
Pinching off a trench traps a void within the trench. Under certain conditions, the void will be filled during the reflow process; however, as the trench becomes narrower, it becomes more likely that the void will not be filled during the reflow process. Such voids are undesirable as they can reduce the yield of good chips per wafer and the reliability of the devices. Therefore, it is desirable to be able to fill narrow gaps with BPSG in a void-free manner. It is also desirable that the processes used to deposit and reflow the BPSG layer be efficient, reliable, and result in a high yield of devices.
Another manufacturing challenge presented by submicron devices is minimizing the overall thermal budget of the IC fabrication process in order to maintain shallow junctions and prevent the degradation of self-aligned titanium silicide contact structures among other reasons. One way to reduce the overall thermal budget of a fabrication process is to reduce the reflow temperature of the BPSG PMD layer to below 800.degree. C. and even more preferably to below 750.degree. C.